Designing an Integrated Circuit (IC) involves performing a sequence of design steps. The initial steps include entering a transistor-level design description or a Hardware Description Language (HDL) based design description into an automated IC design system. Thereafter, a netlist is generated by the IC design system. The netlist is a textual representation of the interconnection of components in the IC. Further, the netlist is simulated to verify that the IC design conforms to specifications. Thereafter, a layout of the IC design is generated either manually or automatically from the netlist. The layout includes technology-level details of design components and parasitics associated with the design. The technology-level details of the design components include, for example, sizes of metal lines, and sizes of polysilicon lines. The parasitics include, for example, capacitances between diffusion regions and the substrate and channel capacitances. A layout netlist is then extracted from the layout of the IC design using automatic tools. Simulations are then run on the extracted netlist to ensure that the layout design conforms to the specifications. In case the extracted netlist does not conform to the specifications, the transistor-level description or the HDL description is modified, to generate a new netlist. Usually, in this process, a number of iterations in the IC design have to be performed.
Performing transistor-level IC design includes sizing of transistors in the IC design. Sizing of transistors include calculating sizes of transistors in the IC design for optimum value of a parameter of the IC design. A parameter of the IC design includes, for example, minimum delay, minimum area and minimum current. Sizing of transistors is laborious and time-consuming process. In case there are a number of iterations in the IC design, the process of sizing the transistors has to be repeated. This may cause significant delay in design tape-out and time-to-market for an integrated circuit.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.